Researcher Name:  Tanay Karnik

Title:  Principal Engineer

Location:  Oregon JF2

Lab:  Circuits Research Lab

Primary Research Area: Low Power Circuits

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Bio:

Tanay Karnik (M'88, SM'04) received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. From 1995 to 1999, he worked in the Strategic CAD Lab at Intel. Since March 1999, he has lead the power delivery, soft error rate, and low power circuits research in the Circuits Research Lab, where he is Principal Engineer and manager of low power circuits research. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 40 technical papers, has 39 issued and 36 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several invited talks and tutorials, and has served on 5 PhD students' committees. He was a member of DTTC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay will be General Chair of ISQED'08 and ICICDT'08.

Publications:

•              B. W. Wah and T. Karnik, "Resource Constrained Design of Artificial Neural Networks Using Comparator Neural Network", Technical Report UILU-ENG-92-2242 CRHC-92-24, November, 1992.

•              T. Karnik and S. M. Kang, "Hierarchical Partitioning of High-level VHDL Structures", VHDL International Users' Forum, pp.36-45, May, 1994.

•              C. H. Chen, T. Karnik and D. G. Saab, "Structural and Behavioral Synthesis for Testability Techniques", IEEE Transactions on CAD, Vol.13, No.6, pp.777-785, June, 1994.

•              T. Karnik, S. Ramaswamy, S. M. Kang and P. Banerjee, "Application of Algorithm Based Fault Tolerance to High-level Synthesis of Signal Flow Graphs", pp.760-776, July, 1994.

•              T. Karnik, D. G. Saab, S. M. Kang, Y. K. Lee and K. H. Kim, "Hierarchical Mixed-level Simulation of VHDL Descriptions", IEEE ASIC Conference, September, 1994.

•              T. Karnik, et al., "High-Level Hot Carrier Reliability-Driven Synthesis", IEEE CICC, May, 1995.

•              T. Karnik and S. M. Kang, "An Empirical Model for Accurate Estimation of Routing Delays in FPGAs", IEEE ICCAD, pp.328-331, November, 1995.

•              T. Karnik, "Microprocessor Layout Method", Book Chapter, Handbook on VLSI, CRC Press, 2000.

•              T. Karnik, et al., "Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 μm", VLSI Circuits Symposium, pp.61-62, June, 2001.

•              T. Karnik, "Power delivery challenges for high-performance low-voltage microprocessors", EPRI Workshop, November, 2001.

•              T. Karnik, et al., "Selective node engineering for chip-level soft error rate improvement [in CMOS]", VLSI Circuits Symposium, pp.204-205, June, 2002.

•              J. Tschanz, et al., "Design optimizations of a high performance microprocessor using combinations of dual-Vt allocation and transistor sizing", VLSI Circuits Symposium, pp.218-219, June, 2002.

•              T. Karnik, et al., "Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors ", IEEE/ACM DAC, pp.486-491, June, 2002.

•              T. Karnik, S. Borkar, V. De, "Sub 90-nm Technologies-challenges and opportunities for CAD", IEEE ICCAD, pp.203-206, November, 2002.

•              F. Paillet and T. Karnik, "Low power and noise tolerant 20 Gb/s CMOS TIA for short-distance optical interconnect ", IEEE SSMSD, pp.49-53, February, 2003.

•              D. Gardner, et al., “Silicon-Based Light Emitting Devices”. Keynote, AVS Conference, March 2003.

•              S. Borkar, et al., “Parameter Variations and Impact on Circuits and Microarchitecture”, IEEE/ACM DAC, pp.338-342, June 2003.

•              J. Xu, et al., “A 10Gbps Ethernet TCP/IP Processor”, HotChips, August 2003.

•              P. Hazucha, et al., “Measurements and analysis of SER tolerant latch in a 90nm dual-Vt CMOS process”, IEEE CICC, pp. 617-620, September 2003.

•              P. Hazucha, et al., “Neutron soft error rate measurement in a 90-nm CMOS process and scaling trends in SRAM from 0.25um to 90nm generation”, IEDM, pp. 523-526, December 2003.

•              T. Karnik, et al., “Probabilistic and Variation-Tolerant Design: Key to Continued Moore's Law”, ACM/IEEE TAU, February 2004.

•              T. Karnik, et al., “Parameter Variations and Impact on Circuits and Microarchitecture”, special session, pp16-17, ISSCC, February 2004.

•              T. Karnik, “High Performance Microprocessor Power Delivery: Challenges and Solutions”, IEEE CPMT Workshop, April 2004.

•              T. Karnik, “Statistical Design for Variation Tolerance: Key to Continued Moore's Law”, IEEE ICICDT, May 2004.

•              G. Schrom, et al., “A 480-MHz, Multi-Phase Interleaved Buck DC-DC Converter with Hysteretic Control”, PESC, June 2004.

•              P. Hazucha, et al., “A 233MHz, 80-87% Efficient, Integrated, 4-Phase DC-DC Converter in 90nm CMOS”, VLSI Circuits Symposium, June 2004.

•              P. Hazucha, et al., “An Area-Efficient, Integrated, Linear Regulator with Ultra-Fast Load Regulation”, VLSI Circuits Symposium, June 2004.

•              T. Karnik, et al., “Impact of Body Bias on Alpha- and Neutron-Induced Soft Error Rates of Flip-flops”, VLSI Circuits Symposium, June 2004.

•              S. Borkar, et al., “Design and reliability challenges in nanometer technologies”, DAC, June 2004.

•              T. Karnik, et al., “Characterization of soft errors caused by single event upsets in CMOS processes”, IEEE Transactions on Dependable and Secure Computing, Vol. 1, Issue 2, April-June 2004.

•              G. Schrom, et al., “Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation”, ISLPED, Aug 2004.

•              P. Hazucha, et al., “Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process”, JSSC, Vol. 39, Issue 9, Sep 2004.

•              T. Chen, et al, “HiSIM: Hierarchical Interconnect-Centric Circuit Simulator”, ICCAD, Nov 2004.

•              S. Rajapandian, et al., “High-Tension Power Delivery: Operating 0.18mm CMOS Digital Logic at 5.4V”, ISSCC, Feb 2005.

•              T. Karnik, “Soft Error Rate: Architecture, Modeling and Circuit Challenges”, Tutorial at ISQED’05.

•              P. Hazucha, et al., “A 233-MHz 80%-87% Efficient Four-Phase DC-DC Converter Utilizing Air-Core Inductors on Package”, JSSC, Vol. 40, Issue 4, April 2005.

•              P. Hazucha, et al., “Area-Efficient Linear Regulator with Ultra-Fast Load Regulation”, JSSC, Vol. 40, Issue 4, April 2005.

•              S. Mitra, et al., “Logic soft errors in sub-65nm technologies design and CAD challenges”, DAC, June 2005.

•              T. Karnik, “Technology impacts on sub-90nm CMOS Circuits Design”, VLSI Conference, India, January 2006.

•              P. Hazucha, et al., “A Linear Regulator With Fast Digital Control For Biasing Of Integrated DC-DC Converters ", ISSCC, Feb 2006.

•              H. Yu, et al., “Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power”, ISLPED, October 2006.

•              C. Long, et al., “Power-efficient PWM DC/DC converters with ZVS control”, ISLPED, October 2006.

•              P. Hazucha, et al., “High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters”, JSSC, Vol. 42, Issue 1, January 2007.

•              J. Tschanz, et al., “Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging”, ISSCC, Feb 2007.

•              J. Xu, et al., “On-Die Supply-Resonance Suppression Using Band-Limited Active Damping”, ISSCC, Feb 2007.

•              P. Hazucha, et al., “Low voltage buffered bandgap reference”, ISQED, March 2007.

•              D. S. Gardner, et al., “Integrated on-chip inductors with magnetic films”, IEEE Transactions on Magnetics, Vol. 43, Issue 6, June 2007.

•              P. Li, et al., “A Delay Locked Loop Synchronization Scheme for High Frequency Multiphase Hysteretic DC-DC Converters”, VLSI Circuits Symposium, June 2007.

•              M. Khellah, et al., “Effect of Power Supply Noise on SRAM Dynamic Stability”, VLSI Circuits Symposium, June 2007.

•              K. Bowman, et al., “Energy-Efficient & Metastability-Immune Timing-Error Detection and Instruction Replay-Based Recovery Circuits for Dynamic Variation Tolerance”, ISSCC, Feb 2008.

•              D. Somasekhar, et al., “2GHz 2Mbit 2T Gain Cell Memory Macro with 128GBytes/sec Bandwidth on 65nm Logic Process Technology”, ISSCC, Feb 2008.