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Priyadarsan Patra
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Priyadarsan Patra, Ph.D.
Intel Research Scientist
Location: Hillsboro, OR
Lab: Validation Research Lab
Microprocessor Technology Labs
Primary Research Area:
Runtime and Post-silicon Validation
Email: Priyadarsan.patra @ intel.com
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Bio:
Dr. Priyadarsan Patra holds a B.S. in Physics and a B.E. in Electronics and Telecommunication Engineering (Indian Institute of Science). He obtained his M.S. in Computer and Information Sciences from the Univ. of Massachusetts, Amherst and a Ph.D. in Computer Science from the Univ. of Texas at Austin. Before joining as a founding member of the Validation Research Lab of Intel's Corporate Technology in early 2006, he had served as a research scientist and senior staff engineer at the Strategic CAD Labs of Intel. He is an IEEE Senior Member. He has received several professional fellowships and awards such as Intel Trail Blazer, Divisional Recognition Awards, SRC/DSTC Mentor awards, and other national and international community awards for research excellence, social leadership, community teaching, and life-long volunteering. He is the founding chair of the Board of Directors of SEEDS (www.seedsnet.org).
“Currently my interest are in many aspects of ‘runtime or lifetime’ validation of processors leading up to platforms. While this area focuses on ‘system survivability’ in the field, it both enables and builds upon silicon correctness in the traditional pre-silicon and post-silicon verification in ways that are power-efficient, modular and scalable. My recent past research at Intel includes modeling and estimation for design exploration of on-chip interconnects, low-power design, high-performance circuit synthesis and optimization, constructive and formalized design refinement and verification, and synthesis of domino logic & register-files. My dissertation involved research on reversible and delay-insensitive computational structures including Rapid-Single-Flux-Quantum circuits with emphasis on low-power. I am a believer in social entrepreneurship: in my spare time I lead a grass-roots organization promoting sustainable, equitable socio-economic and educational development.”
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Peer-reviewed Technical Publications
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K. Chen, S. Malik and P. Patra. Runtime Validation of Memory Ordering Using Constraint Graph Checking. To appear in High Performance Computer Architecture, HPCA 2008.
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Bin Li, P. Patra and L. Peh. Network-on-chip modeling and estimation under process and temperature variation. To appear at 2nd IEEE International Symposium on Networks-on-Chip (NOCS 2008).
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K. Chen, S. Malik and Priyadarsan Patra. Runtime Validation of Transactional Memory Systems. Accepted for publication at ISQED 2008.
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S. Mohanty, E. Kougianos, and P. Patra. “Process Variation Aware Simultaneous Leakage and Dynamic Power Minimization during Nano-CMOS Behavioral Synthesis.” Revised for IEEE Trans. on CAD.
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S. Mohanty, E. Kougianos, D. Ghai and P. Patra. “Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits Under Process Variation.” IWLS 2007.
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Priyadarsan Patra. On the Cusp of a Validation Wall. Invited Article for IEEE Design & Test Magazine. 2007.
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Min Pan, Priyadarsan Patra and Chris Chu. A Novel Performance-Driven Topology Design Algorithm. 12th Asia and South Pacific Design Automation Conference. ASP-DAC 2007.
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Priyadarsan Patra. On the Cusp of a Validation “Wall”. IEEE CEDA Newsletter 2007.
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Priyadarsan Patra, Charles E. Dike, Nasser A. Kurd, and Javed Barkatullah. A mesh-based clock deskew scheme and its formal correctness.
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Kavel Buyuksahin, Priyadarsan Patra, and Farid Najm. Estima: An architectural-level power estimator for multi-ported pipelined register files. In Proc. Int’l Symposium On Low Power Electronics and Design, 2003.
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Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, and Javed Barkatullah. A design for digital, dynamic clock deskew. In Symposia on VLSI Technology and Circuits, 2003.
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B. Chappell, X. Wang, P. Patra, et al. A system-level solution to domino synthesis with 2 GHz application. In Proc. International Conf. Computer Design (ICCD), October 2002.
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Priyadarsan Patra, Unni K. Narayanan, and Taewhan Kim. Phase assignment for synthesis of low power domino circuits. ACM Transactions on Design Automation of Electronic Systems. (Submitted for publication).
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Priyadarsan Patra. Power issues in ULSI circuits. In International Conference on Information Technology, December 2000.
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Mahesh Ketkar, Sachin Sapatnekar, and Priyadarsan Patra. Convexity-based optimization for power-delay tradeoff using transistor sizing. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2000.
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Priyadarsan Patra. Estima: An architecture-level estimator for multi-ported multi-cycle register files. Technical report, Intel Corp., December 2002. Strategic CAD Labs technology.
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Priyadarsan Patra and Xinning Wang. Overview of DCAL logic and timed synthesis. Technical report, Intel Corp., December 2001. Strategic CAD Labs Technology Report.
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B. Chappell, X. Wang, P. Patra, J. Vendrell, S. Rangavirsan, S. Otto, and E. Zahavi. DCAL domino design techniques for efficient synthesis of correct, high speed control logic. In Design and Test Technology Conference (Intel Corp.), 1997.
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Priyadarsan Patra and Unni K. Narayanan. Automated phase assignment for the synthesis of low power domino circuits. In Proc. ACM/IEEE Design Automation Conference, June 1999.
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Priyadarsan Patra, Unni K. Narayanan, and Taewhan Kim. Phase assignment for synthesis of low power domino circuits. In Electronics Letters, June 2001.
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Priyadarsan Patra, Stanislav Polonsky, and Donald S. Fussell. Delay insensitive logic for RSFQ superconductor technology. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1997.
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Priyadarsan Patra and Donald S. Fussell. Efficient delay-insensitive RSFQ circuits. In Proc. International Conf. Computer Design (ICCD), October 1996.
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Priyadarsan Patra and Donald S. Fussell. Power-efficient delay-insensitive codes for data transmission. In Proc. of 28th Hawaii International Conference on System Sciences, Jan 1995.
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Priyadarsan Patra and Donald S. Fussell. Conservative delay-insensitive circuits. In Workshop on Physics and Computation, pages 248-259, November 1996.
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Priyadarsan Patra and Donald S. Fussell. On efficient adiabatic design of MOS circuits. In Workshop on Physics and Computation, pages 260-269, November 1996.
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Priyadarsan Patra. Approaches to Design of Circuits for Low-Power Computation. PhD thesis, The University of Texas at Austin, 1995.
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Priyadarsan Patra and Donald S. Fussell. Fully asynchronous, robust, high-throughput arithmetic structures. In International Conference on VLSI Design. IEEE Computer Society, January 1995.
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Priyadarsan Patra and Donald S. Fussell. Efficient building blocks for delay insensitive circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 196-205, November 1994.
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M. B. Josephs, Priyadarsan Patra, and J. Yantchev. Converting I2C symbols into handshake symbols, Sept. 1992. Technical Note to ESPRIT 6143 - EXACT.
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Book:
S. P. Mohanty, N. Ranganathan, E. Kougianos, Priyadarsan Patra. “Low-Power High-Level Synthesis for Nanoscale CMOS Circuits”. Springer Verlag book to be available in Feb., 2008.
Patents & Inventions
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Priyadarsan Patra. A method of non-intrusive, low-cost, high-bandwidth piggyback debug chip with value add. Invention Disclosure. Intel.
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Priyadarsan Patra. A hardware method for runtime, at-speed shared memory ordering validation. Invention Disclosure. Intel.
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Priyadarsan Patra. Smart Checker ALU for Dynamically Validating Architectures. Approved patent filing in process. Intel.
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Priyadarsan Patra. Spatial Curvature Techniques for Multiobjective Routing Optimization. Patent Pending, 2006. Intel.
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Priyadarsan Patra. A method to reduce network costs and its application to domino circuits. US Patent# 6529861. Intel.
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Priyadarsan Patra and Unni K. Narayanan. Phase optimization for low power domino circuits. US Patent # 6556962. Intel.
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Priyadarsan Patra and Barbara Chappell. Timed synthesis for power optimization of high performance circuits. US Patent# 6721924. Intel.
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Priyadarsan Patra. Technique for High Fidelity and Efficient Random Number Generation. Trade secret.
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H. Yang, X. Wang, and P. Patra. Novel cone-based min-overlap partitioning algorithms for logic. 2000.
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Miscellaneous other research documents authored by Priyadarsan
Other technical or social non-profits/sites created or overseen by Priyadarsan:
ICIT2007.home.comcast.net
www.seedsnet.org
www.iamaor.org
www.orissasociety.org
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