Youfeng Wu
Principal Researcher
Programming Systems Labs
Current research interests include parallelization of single-threaded programs on multiple cores, binary translation, dynamic optimizations, and software/hardware collaborative techniques to enhance future generations of Intel processors.
Bio:
Youfeng is a principal engineer and research team manager in the Programming Systems Lab of Microprocess Technology Labs within the Corporate Technology Group. He received his B.S. degree in Computer Science from Fudan University, Shanghai, China in 1982, and received his M.S. and Ph.D. degrees in Computer Science from Oregon State University, in 1984 and 1988, respectively. Before he joined Intel in 1995, Youfeng worked for Sequent Computer Systems, Inc. for over 7 years. He has more than 20 patents and pending applications. He is a member of IEEE and ACM.
Publications:
Cheng Wang, Victor Ying and Youfeng Wu, “Supporting Legacy Binary Code in a Software Transaction Compiler with Dynamic Binary Translation and Optimization,” CC 2008
Vijay Nagarajan, Ho-Seop Kim, Youfeng Wu, Rajiv Gupta, “Dynamic Information Flow Tracking on Multicores”, Interact-2008
Chuck Zhao, Youfeng Wu, J. Gregory Steffan, Cristiana Amza, “Lengthening Traces to Improve Opportunities for Dynamic Optimization”, Interact-2008
Youfeng Wu, Mauricio Breternitz Jr, Victor Ying, “Impacts of Multiprocessor Configurations on Workloads in Bioinformatics”, 19th International Symposium on Computer Architecture and High Performance Computing, October 24-27, 2007, Gramado, RS, Brazil
Cheng Wang, Shiliang Hu, Ho-Seop Kim, Sreekumar R. Nair, Mauricio Breternitz Jr., Zhiwei Ying, Youfeng Wu: StarDBT: An Efficient Multi-platform Dynamic Binary Translation System. Asia-Pacific Computer Systems Architecture Conference 2007
Cheng Wang, Ho-Seop Kim, Youfeng Wu, Victor Ying: Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection. CGO 2007
Cheng Wang, Wei-Yu Chen, Youfeng Wu, Bratin Saha, Ali-Reza Adl-Tabatabai: Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. CGO 2007
Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo, “Software-Based Transparent and Comprehensive Control-Flow Error Detection”, CGO, 2006
Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, Guido Araujo, “Clustering-Based Microcode Compression.” ICCD 2006
Feng Qin, Cheng Wang, Zhenmin Li, Ho-seop Kim, Yuanyuan Zhou , and Youfeng Wu, “LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks,” Micro-39, 2006.
Qiang Wu, Vijay J. Reddi, Youfeng Wu, Jin Lee, Dan Connors, David Brooks, Margaret Martonosi, and Douglas W. Clark, “Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance”, Micro-38 and was selected by IEEE MICRO Top Picks from Computer Architecture Conferences to appear in the January-February 2006 issue.
Bolei Guo, Youfeng Wu, Cheng Wang, Matthew J. Bridges, Guilherme Ottoni, Neil Vachharajani, Jonathan Chang, David August, “Selective Runtime Memory Disambiguation in a Dynamic Binary Translator”, 15th International Conference on Compiler Construction (CC), March, 2006
Jack Liu, Youfeng Wu, “Performance Characterization of 64bit X86 on 32-bit Applications from Compiler’s Perspective” 15th International Conference on Compiler Construction (CC), March, 2006
Chengliang Zhang, Chen Ding, Mitsunori Ogihara, Yutao Zhong, Youfeng Wu: A hierarchical model of data locality. POPL 2006
Cheng Wang, Victor Ying, Youfeng Wu, “Dynamic Binary Translation and Optimization of Legacy Library Code in a STM Compilation Environment”, Workshop on Binary Instrumentation and Applications 2006
Youfeng Wu, Yong-Fong Lee, “Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection,” Journal of Computer Science and Technology, Science Press, Beijing, China, Vol. 20, No. 5, Sept 2005, pp. 665-675.
Youfeng Wu, Mauricio Breternitz Jr., Herbert Hum, Ramesh Pere, and Jay Pickett, “Enhanced Code Density of Embedded CISC Processors with Echo Technology,” CODES+ISSS 2005 conference, 2005
Steven Carr, Trishul Chilimbi, Chen Ding, Youfeng Wu, “Tutorial on Program Locality Models and Their Use in Memory Performance Optimization” PACT2005 conference.
Youfeng Wu and Jesse Fang, Chapter 5, “Profile-based Speculation”, in book Speculative Execution in High Performance Computer Architectures, edited by David Kaeli and Pew-Chung Yew, 2005, pp. 269-300.
Youfeng Wu, Yong-fong Lee “Explore Free Execution Slots for Accurate and Efficient Profiling on EPIC Processors,” ACSAC’04, Beijing, China, Sept 7 to Sept 9, 2004.
Youfeng Wu, Mauricio Breternitz, Justin Quek, Oma Etzion, and Jesse Fang, “The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators,” CGO?004, Palo Alto, California, March 20-24, 2004.
Youfeng Wu, Mauricio Breternitz, Terri Devor, “Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translators,” 8’th workshop on Interaction Between Compilers and Computer Architectures, Madrid, Spain, Feb. 15, 2004.
Li-Ling Chen and Youfeng Wu, “Aggressive Compiler Optimization and Parallelism with Thread-Level Speculation,” ICCP 2003, Kaohsiung, Taiwan, October 6-9, 2003.
Youfeng Wu, Li-Ling Chen, Roy Ju, and Jesse Fang, “Performance Potentials of Compiler-directed Data Speculation,?ISPASS03, March 2003.
Youfeng Wu, Ryan Rakvic, Li-Ling Chen, .Chyi-Chang Miao, George Chrysos, Jesse Fang, “Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors”, MICRO35, Nov. 2002.
Youfeng Wu, “Efficient Discovery of Regular Stride Patterns in Irregular Programs and Its Use in Compiler Prefetching”, PLDI02, June 2002.
Youfeng Wu, Mauricio Serrano, Rakesh Krishnaiyer, Wei li, Jesse Fang, “Value Profile Guided Stride Prefetching for Irregular Code”, International Conference on Compiler Construction, April 2002.
Youfeng Wu, “Accuracy of Profile Maintenance in Optimizing Compilers”, INTERACT-6 with HPCA, Feb 2002.
Kalyan Muthukumar, Dong-Yuan Chen, Youfeng Wu, Daniel M. Lavery, “Software pipelining of loops with early exits for IA-64”, EPIC-1 with Micro-34, Dec 2001.
Mauricio Serrano and Youfeng Wu, “Memory performance analysis of SPEC2000C for the Itanium processor”, WWC-4 with Micro-34, Dec 2001.
Youfeng Wu, Uptal Benerjee, and Yong-fong Lee, “Calculation of Load Invalidation Rates for Data Speculation,” 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August 8-10, 2001.
Youfeng Wu, Dong-Yuan Chen, and Jesse Fang, “Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction,” ISCA-28, July 2001.
Youfeng Wu, Dong-Yuan Chen, and Jesse Fang, “Integrated Computation Reuse and Value Prediction for Multithreaded Processors”, Workshop on Multithreaded Execution, Architecture and Compilation, in conjunction with Micro-33, Dec. 2000.
Li-ling Chen and Youfeng Wu, “Fast Forward: Aggressive Compiler Optimization with Speculative Multi-Threaded Support”, Workshop on Multithreaded Execution, Architecture and Compilation, in conjunction with Micro-33, Dec. 2000.
Youfeng Wu and Yong-fong Lee, “Accurate Invalidation Profiling for Effective Data Speculation on EPIC Processors,” ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August 8-10, 2000.
Hsien-Hsin Lee, Youfeng Wu, and Gary Tyson, “Quantifying Instruction-Level Parallelism on an EPIC Architecture,” International Symposium on Performance Analysis of Systems and Software, Apr. 2000.
Kingsum Chow and Youfeng Wu, “Feedback-Directed Selection and Characterization of Compiler Optimizations,” Workshop on Feedback Directed Optimizations with MICRO32, Israel, Nov. 1999.
Youfeng Wu, Yong-fong Lee, and Hong Wang, “An Efficient Software-Hardware Collaborative Profiling Technique for Wide-Issue Processors,” Workshop on Binary Translation with PACT99, Newport Beach, California, Oct. 1999.
Youfeng Wu and Yong-Fong Lee, “Comprehensive Redundant Load Elimination for the IA-64 Architecture,” Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing, San Diego, California, August 1999.
Yong-fong Lee and Youfeng Wu, “Hot Region Loop Formation for Effective Software Pipelining and ILP Optimization,” 1997 Intel Software Development Conference, October 21-23, Portland, Oregon.
Youfeng Wu, Pohua Chang, Dong-Yuan Chen, Yong-Fong Lee, “Speculative Load Motion for Wide Issue Speculative Processors,” 1996 Intel Software Development Conference, October 21-23, Scottsdale, Arizona.
P. Chang, D.-Y. Chen, Y.F. Lee, Youfeng Wu, and U. Banerjee, “Bidirectional Scheduling: A New Global Code Scheduling Approach,” Proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing, August 1996.
Youfeng Wu and James Larus, “Static Prediction of branch Probability, branch Frequency and Function Frequency,” 27th Annual International Symposium on Microarchitecture, Dec. 1995.
Youfeng Wu, “Strength Reduction of Multiplications by Integer Constants,” SIGPLAN Notices 30(2): 42-48 (1995)
Su, Bogong, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu, “A Study of Pointer Aliasing for Software Pipelining using Run-time Disambiguation,” Micro-27, 1994, pp112-118.
Youfeng Wu, “Ordering Functions for Improving Memory Reference Locality in Shared Memory Multiprocessor Systems,” 25th Annual International Symposium on Microarchitecture, Dec. 1992.
Youfeng Wu, “The Design of a Test Suite for Parallelizing Translators,” 25th International Conference on System Sciences, Hawaii, Jan. 1992.
Youfeng Wu and Ted Lewis, “Parallelism Encapsulation in C++,” Proc. 1990 International Conference on Parallel Processing, Aug. 1990.
Youfeng Wu and Ted Lewis, “Parallelizing While Loops,” Proc. 1990 International Conference on Parallel Processing, Aug. 1990.
Youfeng Wu and Ted Lewis, “Parallel Algorithms for Decomposable linear Programs,” Proc. 1990 International Conference on Parallel Processing, Aug. 1990.
Youfeng Wu and Ted Lewis, “Parallel Processor Load Balance Through Loop Spreading,” Proc. Supercomputing ‘89, Nov. 1989.
