Pradeep Dubey

Researcher Name:  Pradeep Dubey

Title: Senior Principle Engineer             

Location: Santa Clara, CA

Lab: Microprocessor Technology Lab

Primary Research Area: Innovative Platform Architecture

 

 

 

Bio:

Pradeep Dubey is a senior principal engineer and manager of Innovative Platform Architecture (IPA) in the Microprocessor Technology Lab, part of the Corporate Technology Group. His research focus is computer architectures to efficiently handle new application paradigms for the future computing environment. Dubey previously worked at IBM's T.J. Watson Research Center, and Broadcom Corporation. He was one of the principal architects of the AltiVec* multimedia extension to Power PC* architecture. He also worked on the design, architecture, and performance issues of various microprocessors, including Intel® i386TM, i486TM, and Pentium® processors. He holds over 25 patents and has published extensively. Dr. Dubey received a BS in electronics and communication engineering from Birla Institute of Technology, India, an MSEE from the University of Massachusetts at Amherst, and a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.

 

 

Links:

Selected Publications:

  1. Jatin Chhugani, William Macy, Akram Baransi, Anthony D. Nguyen, Mostafa Hagog, Sanjeev Kumar, Victor W. Lee, Yen-Kuang Chen and Pradeep Dubey, Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture . VLDB 2008, 34th International Conference on Very Large Data Bases, Auckland, New Zealand, Aug 24-30, 2008.
  2. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. Larrabee: A many-core x86 architecture for visual computing. Proceedings of SIGRAPH 2008, 27(3). Los Angeles, California, Aug 12-15, 2008
  3. Yen-Kuang Chen, Jatin Chhugani, Pradeep Dubey, Christopher J. Hughes, Daehyun Kim, Sanjeev Kumar, Victor W. Lee, Anthony D. Nguyen, Mikhail Smelyanskiy, Convergence of Recognition, Mining, and Synthesis Workloads and its Implications . Proceedings of the IEEE, May 2008 (Vol. 96, Issue 5).
  4. Mikhail Smelyanskiy, Victor W Lee, Daehyun Kim, Anthony D Nguyen, Pradeep Dubey, “Scaling Performance of Interior-Point Method on Large-Scale Chip Multiprocessor System”, Supercomputing SC’2007, Nov 10-16, 2007, Reno, California
  5. Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony Nguyen, Yen-Kuang Chen, Pradeep Dubey, “Cache-conscious Frequent Pattern Mining on a Modern Processor”, Proc. of 31st International Conference on Very Large Data Bases (VLDB), pp. 577-588, Aug 2005, Norway (Best Paper Award)
  6. R. Bhaskar, P. Dubey, V. Kumar, A. Rudra, A. Sharma, ``Efficient Galois-Field Arithmetic on SIMD Architectures", accepted for publication in ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2003, June 7-9, San Diego, California.
  7. A. Rudra, P. Dubey, C. Jutla, V. Kumar, J. Rao, P. Rohatgi , ``An Efficient Rijndael Encryption Implementation", Workshop on Cryptographic Hardware and Embedded Systems, CHES 2001, May 13-16, Paris, France.
  8. H. Bassali, J. Chhugani, S. Agarwal, A. Aggarwal, P. Dubey, ``Compression-tolerant Watermarking Scheme", IEEE Conference on Image Processing (ICIP 2000), pp. I-430-433, Sep. 10-13, Vancouver, Canada.
  9. G. Aggarwal, P. Dubey, S. Ghosal, A. Kulshreshtha, and A. Sarkar, ``iPURE: Perceptual and User-friendly REtrieval of Images", IEEE Conference on Multimedia and Expo (ICME 2000), Jul 30-Aug 2, New York, New York.
  10. G. Aggarwal, S. Ghosal, and P. Dubey, ``Efficient query modification for image retrieval", Conference on Vision and Pattern Recognition (CVPR) 2000, June 13-15, 2000, Hilton Head Island, South Carolina.
  11. S. Joshi, P. Dubey, and M. Kaplan, ``A New Parallel Algorithm for CRC Generation", International Conference on Communications (ICC) 2000, vol. 3, pp. 1764-68, June 18-22, 2000, New Orleans, Louisiana.
  12. K. Diefendorff, P. Dubey, R. Hochsprung, and H. Scales, ``AltiVec Extension to PowerPC Accelerates Mediaprocessing", IEEE MICRO, Mar-Apr 2000, pp. 85-95. 
  13. P. Dubey ``Computing Goes Embedded", Invited Paper, Journal of Current Science, Special Issue on Computational Science. Vol. 78, No. 7, pp. 850-851, Apr 2000.
  14. S. Joshi and P. Dubey, ``Some Fast Speech Processing Algorithms using AltiVec Technology", International Conference on Acoustics, Speech, and Signal Processing (ICASSP ‘99), vol. 4, pp. 2135-2138, Phoenix, Arizona, Mar 15-17, 1999.
  15. M. Phillip, K. Diefendorff, P. Dubey, R. Hochsprung, B. Olsson, and H. Scales, "AltiVec(tm) Technology Accelerates Media Processing Across the Spectrum", Hot Chips 10, Stanford University, California, Aug. 16-18, 1998.
  16. T. Conte, P. Dubey, et.al., "Challenges to Combining General-Purpose and Multimedia Processors," IEEE Computer, Dec, 1997, pp. 33-37. 
  17. K. Diefendorff and P. Dubey, ``How Multimedia Workloads will Change Processor Design'', IEEE Computer, Special Issue on Future Processors, Sept, 1997, pp. 43-45.  
  18. V. Vivekanand, K. Gopinath, and P. Dubey, ``Characterizing Vulnerability of Parallelism to Resource Constraints'', High Performance Computing (HiPC '97), Bangalore, India, Dec. 18-21, 1997.
  19. P. Dubey and R. Nair, ``Profile-Driven Sampled Trace Generation'', International Conference of Computer Design (ICCD '96), Austin, Texas, Oct. 7-9, 1996, pp. 217-224.
  20. P. Dubey, A. Krishna, M. Squillante, ``Performance Modeling of a Multithreaded Processor Spectrum,'' Performance Modeling and Simulation of Advanced Computer Systems (eds: Bagchi, Walrand and Zobrist), Gordon and Breach Publishers, Newark, New Jersey.
  21. P. Dubey, K. O'Brien, K. M. O'Brien, and C. Barton, ``Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-assisted Fine-Grained Multithreading,'' IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques (PACT '95), (ACM Order No. 417951) Cyprus, Europe, June 27-29, 1995, pp. 109-121. 
  22. P. Dubey, A. Krishna, and M. Squillante, ``Analytical Performance Modeling for a Spectrum of Multithreaded Processor Architectures'', International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS '95), Durham, North Carolina, Jan.18-20, 1995, pp. 110-122.
  23. P. Dubey and M. Flynn, ``Bubble Propagation model for Pipeline Performance'', Journal of Parallel and Distributed Computing, vol. 23, No. 2, Dec. 1994, pp. 330-337.
  24. P. Dubey, A. Krishna, and M. Flynn ``Analytical Modeling of Multithreaded Pipeline Performance'', Hawaii International Conference on System Sciences (HICSS-27), Hawaii, Jan 4-7, 1994, pp. 361-367.
  25. L. Rauchwerger, P. Dubey, and R. Nair, ``Measuring Limits of Parallelism and Characterizing its Vulnerability to Resource Constraints'', ACM/IEEE International Symposium on Microarchitecture (MICRO-26), Austin, Dec. 1-3, 1993, pp. 105-117.
  26. P. Dubey, G. B. Adams III and M. Flynn, ``Spectrum of Choices: Superpipelines, Superscalars or Multiprocessors'', ACM/IEEE Symposium on Parallel and Distributed Processing, Dallas, Dec. 2-5, 1991, pp. 233-240.
  27. P. Dubey, G. B. Adams III, and M. Flynn, ``Evaluating Performance Tradeoffs Between Fine-Grained and Coarse-Grained Alternatives''. IEEE Transactions on Parallel and Distributed Systems. vol. 6, No. 1, Jan. 1995, pp. 17-27.
  28. P. Dubey, G. B. Adams III and M. Flynn, ``Instruction-Window Size Tradeoffs and Characterization of Program Parallelism'', IEEE Transactions on Computers, Apr. 1994, pp. 431-442. 
  29. P. Dubey and M. Flynn, ``Optimal Pipelining'', Journal of Parallel and Distributed Computing, Jan. 1990, pp. 10-19. 
  30. P. Dubey, ``Single-Thread ILP Limits and Compile-time Multithread Speculation'', ICPP Workshop on Challenges for Parallel Processing, (Invited Paper), Aug 14-18, 1995, pp. 82-89.
  31. P. Dubey, A. Krishna, and M. Flynn, ``Analytical Performance Modeling for a Spectrum of Multithreaded Machines'', Technical Report # RC 19549, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, May 1994.
  32. P. Dubey, G. B. Adams III, and M. Flynn, ``Exploiting Fine-Grain Concurrency: Analytical Insights in Superscalar Processor Design'', Technical Report Number TR-EE 91-31, School of Electrical Engineering, Purdue University, Aug. 1991.
  33. P. Dubey and M. Flynn, ``Branch Strategies : Modeling and Optimizations'', Technical Report No. CSL TR 90-411, Computer Systems Laboratory, Stanford University, Feb. 1990.