Ravi Iyer is a Principal Engineer in the Integrated Platform Architecture Lab in the
Intel's Corporate Technology Group. His research focus is on future SoC and
CMP architectures, innovative cache/memory hierarchies, interconnect fabrics, accelerator design,
emerging workload analysis and performance evaluation. He has published
95+ papers in the above areas. Ravi has also filed 25+ patent applications
He frequently participates in journals, conferences and workshops. He is currently
an associate editor for IEEE TPDS, ACM TACO. He has served on program committees
for many conferences (MICRO, HPCA, PACT, ISPASS, etc) and has been
co-chair for workshops (CAECW, BEACON) and industrial tracks (HPCA). He will
serve as the General Co-Chair for ISCA 2011.
Ravi has been with Intel for 10 years. He previously held positions
in the Systems Technology Lab (working on server architecture and
systems research), in the Communications Technology Lab (working on
IO acceleration research) and in the Enterprise Products Group (working
on server architecture definition and performance). He has made significant
contributions to several innovative technologies (e.g. IOAT, manycore, QoS) and
advanced performance analysis and workload characterization.
Ravi received his Ph.D. in Computer Science from Texas A&M University. He is
an Adjunct faculty member at Portland State University. He collaborates with several
academic groups on architecture research for CMP and SoC platforms. He also mentors
and advises many Ph.D students and has sat on several dissertation committees.
He is a senior member of the IEEE.
Selected Publications
[1] Ravi Iyer, R. Illikkal, O. Tickoo, L. Zhao, P. Apparao, D. Newell, “VM3: Measuring, Modeling and Managing VM Shared Resources” accepted with minor revision for Special Issue on Resource Management in Virtualized Datacenters, Journal of Computer Networks, 2009.
[2] A. Herdrich, R. Illikkal, Ravi Iyer, D. Newell, et al, “Rate-Based QoS Techniques for Cache/Memory in CMP Platforms” to appear in the 23rd ACM International Conference on Supercomputing (ICS 2009).
[3] N. Madan, L. Zhao, N. Muralimanohar, A. Udipi, R. Balasubramonian, Ravi Iyer, S. Makineni, and Don Newell, “Optimizing Capacity and Communication in a 3D Stacked Reconfigurable Hierarchy,” 15th International Symposium on High-Performance Computer Architecture (HPCA 2009), Feb 2009
[4] L. Zhao, Ravi Iyer, J. Moses, R. Illikkal, S. Makineni and D. Newell, “Exploring Large-scale CMP Architectures using ManySim,” IEEE Micro (July/Aug Issue), Aug 2007.
[5] L. Zhao, Ravi Iyer, R. Illikkal, J. Moses, D. Newell and S. Makineni, "CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms,” to appear in the 16th International Conference on Parallel Architectures and Compiler Techniques (PACT 2007), Sept 2007.
[6] P. Apparao, Ravi Iyer and D. Newell, “Implications of Cache Asymmetry on Server Consolidation Performance,” 2008 IEEE Int’l Symposium on Workload Characterization (IISWC 2008), Oct 2008
[7] Ravi Iyer, Ramesh Illikkal, Li Zhao, Srihari Makineni, Don Newell, Jaideep Moses and Padma Apparao, “Datacenter-on-chip Architectures: Tera-Scale Challenges and Opportunities,” Intel Technology Journal (Issue on Tera-Scale Platforms), 2007.
[8] F. Guo, Y. Solihin, L. Zhao and Ravi Iyer, “A Framework for Providing QoS in Chip Multiprocessors,” 40th International Symposium on Micro-architecture (MICRO-40), 2007
[9] Ravi Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, et al., "QoS Policies and Architecture for Cache/Memory in CMP Platforms,” ACM SIGMETRICS, the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2007), San Diego, June 2007.
[10] L. Hsu, S. Reinhardt, Ravi Iyer and S. Makineni, “Communist, Utilitarian, and Capitalist Cache Policies on CMPs: Caches as a Shared Resource,” 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Sept 2006.
[11] R. Huggahalli, Ravi Iyer, S. Tetrick, “Direct Cache Access for High Bandwidth Network I/O,” 32nd International Symposium on Computer Architecture (ISCA 2005), Wisconsin, June 2005.
[12] G. Regnier, S. Makineni, R. Illikkal, Ravi Iyer, D. Minturn, R. Huggahalli and D. Newell, “TCP Onloading for DataCenter Servers: Perspectives and Challenges," IEEE Computer Magazine, Special Issue on Data Centers, (IEEE Computer) November 2004.
[13] Ravi Iyer, “CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," International Conference on Supercomputing (ICS 2004), Saint-Malo, France, June 2004.
[14] S. Makineni and Ravi Iyer, “Architectural Characterization of TCP/IP Packet Processing on the Pentium® M Microprocessor,” 10th International Conference on High Performance Computer Architectures (HPCA 2004), Madrid, Spain, Feb 2004.
[15] Ravi Iyer, N. Amato, L. Rauchwerger and L. Bhuyan, "Comparing the Memory System Performance of the HP V-Class and SGI Origin 2000 using Micro-Benchmarks and Scientific Applications," International Conference on Supercomputing (ICS'99), Rhodes, June 1999.
[16] Ravi Iyer and L. Bhuyan, "Switch Cache: A Framework for Improving the Remote Memory Access Latency for CC-NUMA Multiprocessors," International Symposium on High Performance Computer Architecture (HPCA 1999), Orlando, Jan 1999. Longer version in IEEE Transactions on Computers (2000)
