• Tanay Karnik
• Principal Engineer
• Location (Lab or geography) Oregon
• Primary Research Area Low Power Circuits
• Brief Bio (~250 words) Tanay Karnik received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. From 1995 to 1999, he worked in the Strategic CAD Lab at Intel. Since March 1999, he has lead the power delivery, soft error rate, and low power circuits research in the Circuits Research, Intel Labs, where he is Principal Engineer and manager of low power circuits research. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 40 technical papers, has 46 issued and 32 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several invited talks and tutorials, and has served on 5 PhD students' committees. He was a member of ISSCC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was Technical Program Chair of ASQED’09 and General Chair of ISQED'08, ISQED’09 and ICICDT'08. Tanay is a Senior Member of IEEE and Fellow of ISQED.
• Links, URLs, papers etc