Researcher Name: Partha Kundu
Title: Senior Researcher
Location: Santa Clara
Lab: Platform Architecture
Primary Research Area: Interconnect and memory systems, performance simulation, emulation and performance analysis


BIO
Partha Kundu is a Senior Researcher within Intel Labs in Santa Clara, California. He participated in the development of the Intel® Itanium® instruction-set architecture (ISA) and went on to architect and design the first Itanium based machine (Merced). He was a Principal Architect of the DEC/Alpha EV8 microprocessor, responsible for the memory system architecture. He is recognized as one of the earliest contributors to the field of on-chip interconnects, giving an invited talk at the first 2006 NSF workshop on chip interconnects at Stanford University. Partha served as General Chair of the 3rd IEEE/ACM Networks on Chip Symposium, held at San Diego in May 2009. He was co-editor of the September/October 2007 IEEE Micro special edition on interconnects. He has participated in numerous panels, tutorials and workshops related to interconnection networks and memory systems, at ESWEEK, DATE, DAC and the Intel Developers Forum. He holds an M.S. degree from the State University of New York, Stony Brook.


PUBLICATIONS
• A 4.6Tbits/s 3.6Ghz Single-Cycle NoC Router with a Novel Switch Allocator in 65nm CMOS. In the proceedings of International Conference on Computer Design (ICCD), October 2007. Lake Tahoe, CA
Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj Jha
• Integration Challenges and Tradeoffs for Tera-scale Architectures, Intel Technology Journal, Vol. 11, Issue 03, August 22, 2007.
M. Azimi, N. Cherukuri, D. N. Jayasimha, A. Kumar, P. Kundu, S. Park, I. Schoinas, A. S. Vaidya.
• Express Virtual Channels: Towards the Ideal Interconnection Fabric. In the Proceedings of International Symposium on Computer Architecture (ISCA), San Diego, CA, USA, June 2007. Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj Jha
Also appeared in special issue on IEEE Micro’s Top Picks from 2007 Computer Architecture Conference papers. (January/February 2008 issue).
• Hybrid Transactional Memory. In the Proceedings of ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New York, USA, March 2006.
Sanjeev Kumar, Chris Hughes, Partha Kundu, Anthony T. Nguyen
• Making Parallel Programming Easier using a Hybrid Transactional Memory Scheme. At Intel Programming Conference on Parallel Programming, Santa Clara, CA, January 2005.
• A case for shared instruction cache on chip multiprocessors running OLTP
Published in ACM SIGARCH Computer Architecture News Volume 32 , Issue 3 (June 2004) and MEDEA workshop held in conjunction with PACT, Sept. 2003, New Orleans, USA.
Partha Kundu, Murali Annavaram, Trung Diep and John Shen.
• Overview of the Merced Microarchitecture
First paper on the Itanium Architecture family’s ISA.
Intel’s Design and Test and Technology Conference (DTTC), July 1996, Chandler, AZ, USA.
H. Sharangpani, K. Arora, M. Corwin, J. Fu, S. Kim, P. Kundu, M. Poplingher, T-Yu Yeh

SELECTED TALKS
• Invited talk at Princeton University's first Computer Arch (CArch) day in April 2009. Slides at: www.princeton.edu/~carch/carchday2009/kundu.pdf
• Invited Talk at On and Off Chip Interconnects (OCIN) workshop held Dec. 6-7, 2006 at Stanford University (sponsored by NSF).
Video and slides at : www.ece.ucdavis.edu/~ocin06/program.html

PATENTS
• Method and apparatus for register stack implementation using micro-operations.
• Method and apparatus to reduce spill and fill overhead in processor with a register backing store.
• A method and system to provide user-level multi-threading.
• Hybrid hardware and software implementation of transactional memory access.
• Scatter gather intelligent memory architecture for unstructured streaming data on multiprocessor systems.
• A novel low latency, high throughput switch allocator for on-chip 2D interconnection networks.
• Express virtual channels in a packet switched on-chip interconnection network.
PROFESSIONAL ACTIVITIES
• co-General Chair for IEEE/ACM Networks-on-Chip Symposium (NOCS) at San Diego, CA, USA, May 10 - 13, 2009
• Guest editor special issue of IEEE Micro magazine on: “On Chip Interconnects for Multicore”. In September/October 2007 issue (Vol. 27, No. 5)
• On technical program committee (TPC) of SuperComputing 2009, Networks on Chips Symposium (NOCS) 2007, 2008.
Session Chair and Program Committee member for Design Automation and Test in Europe (DATE), March 2008 conference in Munich, Germany.
TPC member DATE 2009 (Nice, France).
• National Science Foundation (NSF) panelist to review research proposals for US government funding in the field of Computer Sciences
• Member of Intel’s Architecture IP (patent) committee (since 2001)
• Senior Member of ACM, IEEE